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Espressif Systems /ESP32-C3 /SPI0 /USER

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Interpret as USER

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CS_HOLD)CS_HOLD 0 (CS_SETUP)CS_SETUP 0 (CK_OUT_EDGE)CK_OUT_EDGE 0 (USR_DUMMY_IDLE)USR_DUMMY_IDLE 0 (USR_DUMMY)USR_DUMMY

Description

SPI0 user register.

Fields

CS_HOLD

spi cs keep low when spi is in done phase. 1: enable 0: disable.
CS_SETUP

spi cs is enable when spi is in prepare phase. 1: enable 0: disable.
CK_OUT_EDGE

the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.
USR_DUMMY_IDLE

spi clock is disable in dummy phase when the bit is enable.
USR_DUMMY

This bit enable the dummy phase of an operation.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data